ducky.cpu.registers module¶
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class
ducky.cpu.registers.Registers[source]¶ Bases:
enum.IntEnum-
CNT= <Registers.CNT: 33>¶
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FP= <Registers.FP: 30>¶
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IP= <Registers.IP: 32>¶
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R00= <Registers.R00: 0>¶
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R01= <Registers.R01: 1>¶
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R02= <Registers.R02: 2>¶
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R03= <Registers.R03: 3>¶
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R04= <Registers.R04: 4>¶
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R05= <Registers.R05: 5>¶
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R06= <Registers.R06: 6>¶
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R07= <Registers.R07: 7>¶
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R08= <Registers.R08: 8>¶
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R09= <Registers.R09: 9>¶
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R10= <Registers.R10: 10>¶
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R11= <Registers.R11: 11>¶
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R12= <Registers.R12: 12>¶
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R13= <Registers.R13: 13>¶
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R14= <Registers.R14: 14>¶
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R15= <Registers.R15: 15>¶
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R16= <Registers.R16: 16>¶
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R17= <Registers.R17: 17>¶
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R18= <Registers.R18: 18>¶
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R19= <Registers.R19: 19>¶
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R20= <Registers.R20: 20>¶
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R21= <Registers.R21: 21>¶
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R22= <Registers.R22: 22>¶
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R23= <Registers.R23: 23>¶
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R24= <Registers.R24: 24>¶
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R25= <Registers.R25: 25>¶
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R26= <Registers.R26: 26>¶
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R27= <Registers.R27: 27>¶
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R28= <Registers.R28: 28>¶
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R29= <Registers.R29: 29>¶
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REGISTER_COUNT= <Registers.REGISTER_COUNT: 34>¶
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REGISTER_SPECIAL= <Registers.FP: 30>¶
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SP= <Registers.SP: 31>¶
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