ducky.cpu.registers module¶

class ducky.cpu.registers.RegisterSet[source]¶: Bases: object

class ducky.cpu.registers.Registers[source]¶

Bases: enum.IntEnum

CNT = <Registers.CNT: 33>¶

FP = <Registers.FP: 30>¶

IP = <Registers.IP: 32>¶

R00 = <Registers.R00: 0>¶

R01 = <Registers.R01: 1>¶

R02 = <Registers.R02: 2>¶

R03 = <Registers.R03: 3>¶

R04 = <Registers.R04: 4>¶

R05 = <Registers.R05: 5>¶

R06 = <Registers.R06: 6>¶

R07 = <Registers.R07: 7>¶

R08 = <Registers.R08: 8>¶

R09 = <Registers.R09: 9>¶

R10 = <Registers.R10: 10>¶

R11 = <Registers.R11: 11>¶

R12 = <Registers.R12: 12>¶

R13 = <Registers.R13: 13>¶

R14 = <Registers.R14: 14>¶

R15 = <Registers.R15: 15>¶

R16 = <Registers.R16: 16>¶

R17 = <Registers.R17: 17>¶

R18 = <Registers.R18: 18>¶

R19 = <Registers.R19: 19>¶

R20 = <Registers.R20: 20>¶

R21 = <Registers.R21: 21>¶

R22 = <Registers.R22: 22>¶

R23 = <Registers.R23: 23>¶

R24 = <Registers.R24: 24>¶

R25 = <Registers.R25: 25>¶

R26 = <Registers.R26: 26>¶

R27 = <Registers.R27: 27>¶

R28 = <Registers.R28: 28>¶

R29 = <Registers.R29: 29>¶

REGISTER_COUNT = <Registers.REGISTER_COUNT: 34>¶

REGISTER_SPECIAL = <Registers.FP: 30>¶

SP = <Registers.SP: 31>¶